← All writing

Design report / ASIC

Designing a neuromorphic NPU

A report outline for a first Hack Club ASIC design, from motivation and architecture to verification and evidence.

Unpublished draft outlineTechnical content is awaiting verified source material. This page is excluded from RSS and search indexing.
Designing a neuromorphic NPU — project illustration
Project illustration

Editorial draft. This is the structure for the forthcoming report, not a completed technical account. Design details, diagrams, source links, and measured results are awaiting verified material.

Overview and motivation

Document the intended application and the reason for exploring a neuromorphic NPU through Hack Club ASIC. State what the design is intended to achieve and what this iteration will test.

The problem and workload

Describe the workload, input and output shapes, constraints, and host baseline. Explain which bottleneck makes dedicated hardware worth investigating.

Architecture and datapath

Add a reviewed block diagram of the actual design. Trace a single unit of work through the datapath, identifying where data is stored and where computation happens.

ARCHITECTURE FIGURE AWAITING VERIFIED DESIGN

Figure 1. Reserved for the reviewed architecture diagram. No architecture is implied by this placeholder.

Numerical representation

Specify neuron and synapse representations, value ranges, update rules, rounding, saturation, and overflow behavior. Include small independent examples with expected outputs.

Control, memory, and communication

Describe the real control sequence, storage layout, interface signals, backpressure, reset behavior, and data movement. Separate implemented interfaces from planned extensions.

RTL and module structure

Map the actual modules to their responsibilities and interfaces. Add source-linked, syntax-highlighted excerpts here after review.

Simulation and verification

Explain the reference model, directed and randomized tests, numerical checks, and any simulation waveforms. Give reproducible commands and identify the revision tested.

Results and limitations

Publish only results backed by artifacts. Distinguish estimates, simulation, synthesis, timing analysis, and hardware measurements.

Evidence Current publication state
Reviewed architecture Not supplied
Source repository and revision Not supplied
Simulation artifacts Not supplied
Synthesis and timing reports Not supplied
Hardware measurements Not supplied

Tradeoffs and next iteration

Connect each proposed improvement to an observed limitation. Keep open questions visible rather than presenting future work as completed work.

References and acknowledgements

Add the repository, design references, and acknowledgements after confirming the exact sources and attribution.

Back to writing ↗